1. Field of the Invention
The present invention generally relates to an image sensor and more particularly to a method for manufacturing a complementary metal-oxide-silicon (CMOS) image sensor which can prevent generation of dark current.
2. Discussion of the Related Art
An image sensor is a semiconductor device which can transform an optical image into an electrical image and may be a CMOS image sensor or a charge-coupled device (CCD). A multitude of individual metal-oxide-silicon (MOS) capacitors, each of which can store and convey a charge carrier, are arranged in very close proximity to form a charge-coupled device. CMOS image sensors are devices which have MOS transistors respectively formed corresponding to pixels by CMOS technology, using a control circuit and a signal processing circuit as a peripheral circuit, and adopt switching technology which allows outputs to be sequentially detected through the MOS transistors.
Charge-coupled devices are known to have drawbacks, including a complicated driving manner, high electric power consumption, a complicated manufacturing process resulting from many mask processes, and a difficulty of manufacturing a single chip CCD due to the impediment of devising a signal processing circuit that can be implemented in such a chip. A continued development of CMOS image sensors by use of sub-micron CMOS technology intends to overcome these drawbacks.
There are several different types of pixel structures for CMOS image sensors. Representatively commercialized types include a pixel of a three-transistor (3-T) structure comprising three basic transistors and one photodiode and a pixel of four-transistor (4-T) structure comprising four basic transistors and one photodiode. A conventional 3-T type CMOS image sensor is shown in FIG. 1, in which the unit pixel of the 3-T type CMOS image sensor comprises three transistors and one photodiode PD.
Referring to FIG. 1, each of the three transistors comprises a reset gate Rx for resetting optical charges accumulated in the photodiode PD, a drive gate Dx serving as a source follower buffer amplifier, and a select gate Sx for addressing through switching. Here, a photodiode region A comprising the photodiode PD contains no salicide, while a logic region, i.e., the areas other than the photodiode region A, is formed with salicide. Salicide is used in the formation of the logic region so that the operating speed of the transistors Rx, Dx, and Sx can be increased, but there can be no salicide in the photodiode region A since salicide would reflect light received by the photodiode PD to reproduce an image.
Referring to FIG. 2, showing the photodiode PD and the reset gate Rx along line I-I′ of FIG. 1, the 3-T type CMOS image sensor comprises a gate oxide film 2 formed on a semiconductor layer 1 having a high-concentration p++ layer, a p-epitaxial (p-epi) layer, and a field oxide film 9 stacked therein, a reset gate 3 formed on the gate oxide film 2, and an photodiode impurity area (PDN) 4 formed in a photodiode region A at one side of the reset gate 3. An n+ area 5 is formed at the other side of the reset gate 3 in the semiconductor layer 1, and spacers 6 are formed at both sides of the reset gate 3. An n− area 7 is formed under the spacer 6 near the n+ area 5 in the semiconductor layer 1. As described above, a salicide film 8 cannot be formed in the photodiode region A and must be exclusively formed in the logic region. Thus, the salicide film 8 is excluded from the area of the reset gate 3 belonging to the photodiode region A and is formed only in the areas of the reset gate 3 and the n+ area 5 belonging to the logic region.
A method for manufacturing a conventional CMOS image sensor will be described with reference to FIGS. 3A-3H, in which each drawing shows the photodiode region (left side, corresponding to line I-I′ of FIG. 1) and the logic region (right side, corresponding to line II-II′ of FIG. 1). Here, it should be noted that a typical image sensor includes a semiconductor layer having a high-concentration p++ layer and a p-epitaxial layer in a stacked formation, which will be collectively referred to as a semiconductor layer 10.
Initially, as shown in FIG. 3A, an active area is defined by forming a local field oxide film 11 on the semiconductor layer 10 through an oxidation process, for example, a thermal oxidation process. Then, an oxide film-based gate insulating film 12 is formed to a thickness of about 50 Å on the entire surface of the active area. Next, after depositing a single or multiple conductive films of polysilicon, tungsten, or the like, gate electrodes 13 are formed by patterning through the gate conductive film in a patterning process using a mask for forming a gate electrode pattern. The gate electrode 13 formed in the photodiode region is a reset gate electrode, and the gate electrode 13 formed in the logic region is a drive gate electrode or select gate electrode. Ions are then implanted using an ion implantation mask (not shown) for opening the photodiode region, such that an N-type photodiode impurity area 14 is formed in the semiconductor layer 10 so as to be aligned at one side of the reset gate electrode. In addition, low-concentration impurity ions are implanted into the active area excluding the photodiode region, for example, the semiconductor layer 10 between the reset gate electrode and the drive gate electrode, thereby forming n− areas 15 which will become low-concentration source/drain areas of the transistors.
Then, as shown in FIG. 3B, a spacer-forming insulating film 16 is formed on the entire surface of the gate insulating film 12 and the gate electrodes 13. The spacer-forming insulating film 16 is formed by sequentially depositing, for example, a SiO2 film of 200 Å and a SiN film of 800 Å.
Next, as shown in FIG. 3C, the spacer-forming insulating film 16 is primarily etched to remain at both sides of the gate electrode 13 after primary etching, thereby forming spacers 16a. Primary etching is controlled to have a SiN:SiO2 etching ratio of 1.62:1. As the device is decreased in size, the length of the gate is gradually decreased, causing a narrow line effect. The narrow line effect is a phenomenon of irregular increase in the resistance of the device, and a salicide process is performed to alleviate the narrow line effect. Salicide is a material having a low resistance and is formed by reaction of silicon and metal. In particular, salicide containing titanium suffers from an agglomeration phenomenon in which titanium incompletely reacts with silicon, whereby titanium and silicon remain in an amorphous shape. Thus, in order to avoid such a phenomenon, the spacers 16a must be over-etched so as to open upper side surfaces of the gate electrode 13. Typically, in a 0.25 μm process, the over-etched spacers must have a length of 250 Å or more; in a 0.18 μm process, the over-etched spacers must have a length of 500 Å or more.
For this reason, the spacers 16a are over-etched as shown in FIG. 3D. The over-etching process is performed by two steps, whereby after initial etching is performed under the condition that only the SiN film can be selectively etched, subsequent etching is performed at a SiN:SiO2 etching ratio of 3.53:1. Thus, the SiN film is completely removed, and the SiO2 film remains at a thickness of about 25 Å. Thus, both sides of the gate electrode 13 are formed with insulating films, each having a height of 75 Å, comprising the SiO2 film of 25 Å and the lower gate insulating film 12 of 50 Å.
As described above, over-etching of the spacers is performed for the purpose of allowing easy formation of salicide and is generally used by a logic process. In the CMOS image sensor, however, the semiconductor layer 10 of the photodiode region is damaged during over-etching of the spacers, causing dark current generation.
Thereafter, as shown in FIG. 3E, high-concentration ions are implanted into the active area excluding the photodiode region using the spacers 16a as a mask, thereby forming an n+ area 17 which will become high-concentration source/drain areas of the transistors, and then a salicide-protecting insulating film 18 is formed over the entire surface of the resultant. To complete the manufacture a conventional CMOS image sensor, photoresist 19 is formed as shown in FIG. 3F, so as to cover the photodiode region; as shown in FIG. 3G, the salicide-protecting insulating film 18 is isotropically etched using the photoresist 19 as the mask; and finally, the photoresist 19 is removed as shown in FIG. 3H. Although not shown in the drawings, a salicide film is formed on the gate electrode 13 and the n+ areas 17 by performing a salicide process using the salicide-protecting insulating film 18 as the mask.
In the method for manufacturing the conventional CMOS image sensor as described above, salicide must be formed on the gate electrode in the logic region to reduce the resistance of transistors, and, in this case, the spacers must be over-etched so as to open the sides of the gate electrode in order to prevent the agglomeration phenomenon, in which silicon incompletely reacts with metal of a high melting point and remains in an amorphous shape. With the conventional method, however, the semiconductor layer in the photodiode region is damaged during the over-etching process, thereby causing dark current.